A Fast Clock Scheduling for Peak Power Reduction in LSI
نویسندگان
چکیده
منابع مشابه
A Clock-Gating Method for Low-Power LSI Design
This paper describes an automated layout design technique for the gated-clock design. Two issues must be considered for gated-clock circuits to work correctly. One is to minimize the skew for gated-clock nets. The other is to keep timing constraints for enable-logic parts. We propose the layout design technique to taking these things into consideration. We developed GatedClock Tree Synthesizer ...
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ژورنال
عنوان ژورنال: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
سال: 2008
ISSN: 0916-8508,1745-1337
DOI: 10.1093/ietfec/e91-a.12.3803